module t_cp2001 ();

reg [1:0] ADDR;
reg [7:0] DINPUT;
wire [7:0] DOUTPUT;
reg nRD, nWE, nCS, nRESET, CLK;
wire nIDLE;

task taskSetRegisterAny;
input [7:0] inputDataToDUT;
input [1:0] registerSelector;
begin
	/*Load Data Register*/
	ADDR = 2'b00;
	DINPUT = inputDataToDUT;
	nCS = 1'b0;
	#5;
	nWE = 1'b0;
	#5;
	nWE = 1'b1;
	#5;
	nCS = 1'b1;
	#5;
	/*Execute SETX-CMD*/
	ADDR = 2'b01;
	DINPUT = {6'b000001, registerSelector};
	nCS = 1'b0;
	#5;
	nWE = 1'b0;
	#5;
	nWE = 1'b1;
	#5;
	nCS = 1'b1;
	#5;
end
endtask

task taskGetRegisterAny;
input [1:0] registerSelector;
begin
	/*Load Command - GET?*/
	ADDR = 2'b01;
	DINPUT = {6'b000011, registerSelector};
	nCS = 1'b0;
	#5;
	nWE = 1'b0;
	#5;
	nWE = 1'b1;
	#10;
	/*Export data to port*/
	ADDR = 2'b10;
	#5;
	nRD = 1'b0;
	#5;
	nRD = 1'b1;
	#5;
	nCS = 1'b1;
	#5;
end
endtask

task taskCalc;
input [2:0] inputCommandToDUT;
begin
	ADDR = 2'b01;
	DINPUT = {5'b00010, inputCommandToDUT};
	nCS = 1'b0;
	#5;
	nWE = 1'b0;
	#5;
	nWE = 1'b1;
	#5;
	nCS = 1'b1;
	#5;
end
endtask

task taskReset;
begin
	ADDR = 2'b01;
	DINPUT = 8'h00;
	nCS = 1'b0;
	#5;
	nWE = 1'b0;
	#5;
	nWE = 1'b1;
	#5;
	nCS = 1'b1;
	#5;
end
endtask

always
begin
	ADDR = 2'b00;
	DINPUT = 8'h00;
	nRD = 1'b1; 
	nWE = 1'b1;
	nCS = 1'b1;
	nRESET = 1'b0;
	CLK = 1'b0;
	#5;
	nRESET = 1'b1;
	#5;
	/*Test code start*/
	
	/*Test Case 1: SET/GET register*/
	/*
	taskSetRegisterAny(8'h68, 2'b00);
	#15;
	taskGetRegisterAny(2'b00);
	*/
	
	/*Test Case 2: Calculate sine and cosine value of pi/4, using Q1.6 notation*/
	taskSetRegisterAny(8'h27, 2'b00);
	taskSetRegisterAny(8'h00, 2'b01);
	taskSetRegisterAny(8'h32, 2'b10);
	taskCalc(3'b101);
	#32
	taskGetRegisterAny(2'b00);
	taskGetRegisterAny(2'b01);
	taskGetRegisterAny(2'b10);
	taskReset;
	
	
	/*END*/
	#64;
	$stop;
end

always
begin
	CLK = ~CLK;
	#1;
end

cp2001 DUT (.ADDR(ADDR), .DINPUT(DINPUT), .DOUTPUT(DOUTPUT), .nWE(nWE), .nRD(nRD), .nRESET(nRESET), .CLK(CLK), .nCS(nCS), .nIDLE(nIDLE));

endmodule
